Optimization of PFC cuk converter parameters design for\r\nminimization of THD and voltage ripple

This paper presents the optimization of PFC Cuk converter parameter design
\r\nfor the minimization of THD and voltage ripple. In this study, the PFC Cuk
\r\nconverter is designed to operate in discontinuous conduction mode (DCM) in
\r\norder to achieve almost unity power factor. The passive components, i.e.,
\r\ninductor and capacitor are designed based on switching frequency and
\r\nresonant frequency. Nevertheless, the ranges of duty cycle for buck and boost
\r\noperations are 0<D<0.5 and 0.5<D<1, respectively for the output voltage
\r\nvariation of the converter. The principle of the parameters design
\r\noptimization is based on the balancing energy compensation between the
\r\ninput capacitor and output inductor for minimization of THD current. In
\r\naddition, the selection of high output capacitance will minimize the output
\r\nvoltage ripple significantly. A 65 W PFC Cuk converter prototype is
\r\ndeveloped and experimentally tested to confirm the parameters design
\r\noptimization principle. The experimental results show that the THD current
\r\nis reduced to 4.5% from 61.3% and the output voltage ripple is reduced to 7
\r\nV from 18 V after parameters optimization are realized. Furthermore, it is
\r\nconfirmed that the output voltage ripple frequency is always double of the
\r\ninput line frequency, 50 Hz and the output voltage ripple is always lower
\r\nthan the maximum input voltage ripple